Design for Manufacturability
  • W. Maly, J. Gempel, D. Korzec, A.P. Piotrowski and M. Syrzycki, Statistical Simulation of VLSI IC Cell, Proc. of IEEE International Conference on Computer Aided Design, pp.254-255, 1983.
  • M. Syrzycki, Modelling of Spot Defects in MOS Transistors, 1987 International Test Conference ITC'87, Washington, D.C., pp.148-157, September 1987.
  • M. Syrzycki, Modeling of Gate Oxide Shorts in MOS Transistors, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.8, No.3, pp.193-202, March 1989.
  • M. Syrzycki, S. Naseh and T. Liang, Design for Manufacturability of Analog CMOS VLSI Circuits by Layout Optimization, Micronet Network of Centres of Excellence Workshop, p.47-48, Ottawa, April 6, 1998.
  • R. Ockey, M. Syrzycki, Layout-Related Design for Manufacturability of CMOS Comparators for Analog-to-Digital Converters, Micronet Network of Centres of Excellence Workshop, p.86-87, Ottawa, Apr 26-27, 1999.
  • R. Ockey, M.S yrzycki, Optimization of a Latched Comparator for High-Speed Analog-to-Digital Converters, IEEE 1999 Canadian Conference on Electrical and Computer Engineering, CCECE'99, Edmonton, Alberta, May 9-12, 1999.
  • K. Henderson and M. Syrzycki, Physical Design of Differential-Mode CMOS Transmitters and Receivers, Micronet Network of Centres of Excellence 10th Anniversary Workshop, p.15-16, Ottawa, April 27-28, 2000.
  • R. Ockey, M. Syrzycki, Analysis of Manufacturability Factors for Analog CMOS A/D Converter Building Blocks, Analog Integrated Circuits and Signal Processing International Journal, Kluwer Academic Publishers, Vol.26, No.3, pp.239-255, Mar. 2001.
  • P. Khademsameni, M. Syrzycki, Manufacturability Analysis of Analog CMOS ICs through Examination of Multiple Layout Solutions, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 3-11, Vancouver, British Columbia, November 6-8, 2002.

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