Maryam Keyvani
   M.A.Sc student
 

    Education:

    M.A.Sc in Communication Networks (in progress)
    Member of: Communication Networks Laboratory
    Supervisors: Dr. Ljiljana Trajkovic
                       Dr. Steve Hardy
    School of Engineering Science
    Simon Fraser University
 

    B.Sc  in Electrical Engineering, Power (Feb 1998)
    Faculty of Engineering
    University of Tehran

    Office:

    Communication Networks Lab
    School of Engineering Science
    Simon Fraser University
    8888 University Drive, Burnaby, BC
    V5A 1S6, Canada
    Tel: (604) 291-3831
    email: mkeyvani@cs.sfu.ca

    Research:

M.A.Sc thesis description:

Hardware implementation of a high-speed symmetric crossbar switch:
M.A.Sc. student Maryam Keyvani, B.A.Sc student Arash Haidari-Khabbaz, co-supervisors Dr. Stephen Hardy and Dr. Ljiljana Trajkovic

We are working on a hardware implementation of a crossbar packet switch for high-speed data networks. We use VHDL to describe our design, and the ALTERA MAX+PLUS II tools to simulate it, and the FLEX 10KE ALTERA chips for implementation. The switch has 8 input and 8 output ports, with input queuing. The switch is capable of handling fixed sized packets, such as ATM cells.

The switch architecture consists of input buffers, input port controllers, destination look up tables, a centralized scheduler, and a crossbar fabric. The packets first arrive (ingress) to the input ports of the switch. There, serial data is shifted into a serial shift register. As soon as a byte of data is received, it is loaded into a FIFO queue. Each input port has a controller that queues the header of each packet in a separate FIFO buffer, extracts address information from the header of the packet, and sends it to a programmable look up table (LUT). The LUT returns a destination port address. Based on this address, the controller sends a request to the centralized scheduler. The scheduler receives requests from all input ports and grants them based on a simple two-dimensional ripple-carry arbiter architecture called Rectilinear Propagation Arbiter (RPA). A round robin priority scheme ensures fairness to all the input ports. Once a grant is issued, the crossbar fabric is configured to map the input port that received a grant to its output port destination. The outgoing (egress) packets are stored into another shift register and then shifted serially to the output link.

Publication:

N. Alborz, M. Keyvani, M. Nikolic, and Lj. Trajkovic, ``Simulation of packet data networks using OPNET,'' OPNETWORK 2000, Washington, DC, Aug. 2000.

Websites of interests:

Tiny Tera Switch

ATM forum

HOT interconnects symposium

    Courses taken at SFU:

ENSC351: Real Time and Embedded Systems
ENSC350:Digital Systems Design
ENSC427:Communication Networks
ENSC851:Introduction to Microelectronics and Fabrication
ENSC802:Stochastic Systems
ENSC894: Special Topics I : High-Speed Networks
CMPT816:Theory of Communication Networks
ENSC891: Directed studies I: VLSI Systems Design

    TA experiences:

    Summer 1999:

CMPT250: Introduction to Computer Architecture
Instructor: David Gerhard
Responsibilities: Tutorials for Synopsys software and VHDL language, office hours, marking, supervising the lab and holding a lecture.

CMPT250: Introduction to Computer Architecture
Instructor:Tony Dixon
Responsibilities: Tutorials for Synopsys software and VHDL language, office hours, marking and supervising the lab.

CMPT150: Introduction to Computer Design
Instructor: David Gerhard
Responsibilities: Tutorials for Design Works software, tutorials for HC11 Assembler (PE microcomputers package), Assembly language tutorials,
                         tutoring sessions, office hours and marking.

    Personal:

Links to Iran:

• Iranian


• persepolis

Photo album