Victor Gusev Lesau

Graduate Student

Intelligent / Distributed Enterprise
Automation Laboratory
School of Engineering Science
Simon Fraser University
Burnaby, BC V5A 1S6 Canada 

Tel: (778) 239-5047
Internet: victor_lesau[at]
FB: PR_Hardware



2008 - present
Computer and Systems Engineering
School of Engineering Science
Simon Fraser University
Burnaby, BC, Canada
MASc student in Engineering Science
- OS-level control of partial reconfiguration in Xilinx FPGAs
- Linux on FPGAs, kernel and drivers
- Distributed embedded systems, hardware-software co-design

2001 - 2006
Electrical Engineering
McMaster University
Hamilton, ON, Canada
Received Bachelors degree in Electrical Engineering
- Java bytecode hardware processor implementation

Professional Experience

2006 - present
Product Design Engineer
PMC-Sierra Inc.
Burnaby, BC, Canada
- Requirements, design and verification of channelized ODU Transmit Framer IP and Frame Alignment IP, part of 150M+ gates 40nm OTN ASSP
- Full development cycle from requirements to design, implementation, verification, emulation and testing support of a channelized Transparent Generic Framing Procedure (GFP-T) IP with virtual group-to-channel mapping, part of 65M+ gates 65nm ASSP
- 800K+ gates GFP-T/OTN subsystem supervision through code updates, verification/synthesis/emulation/validation stages
- Verification/validation (10M+ gates ASSP)

2004 - 2005
R&D Internship
Rogers Wireless Inc.
Toronto, ON, Canada
- Software Defined Radio (FPGA prototyping, baseband modulation)
- EDGE/GPRS/EGPRS Matlab Simulation (algorithms and visualization)
- Ultra-Wideband (UWB) Radio (measurements, part of approval of UWB in Canada)

2004 and 2006
Teaching Assistant
McMaster University
Hamilton, ON, Canada
- Engineering Project course
- Introduction to Programming for Engineers course

Research Interests

  • Dynamic partial reconfiguration of FPGAs for control applications
  • Linux on FPGAs, kernel and drivers
  • Distributed computer and embedded systems
  • Applications of the above in wireless and wireline communications

Professional Skills


  • Working knowledge of System Verilog, Verilog, VHDL, Specman/e
  • FPGA and ASSP/ASIC architecture, digital design, implementation, verification, emulation and lab validation
  • Hardware-software co-design on statically and partially reconfigurable FPGA systems
  • Processors: Microblaze, Plasma, VHDL implementation of hardware multi-threading
  • Familiar with MIPS and ARM assembly


  • Working knowledge of Linux kernel and device drivers development, Cadence Design Tools, Specman, Xilinx ISE/EDK/PlanAhead, Modelsim, Altera Quartus II, PSpice, LabView, Matlab, Maple, AutoCAD, VMware, Visio, UML

Operating Systems

  • Experienced in Windows, Linux, Unix
  • Working knowledge of uC/OS-II RTOS, PetaLinux, uCLinux
  • Familiar with VxWorks


  • Working knowledge of Tcl, e, C, Bash, C-Shell, Matlab, Visual Basic, HTML
  • Familiar with Ruby on Rails, PHP, and MySQL

Test Equipment

  • Working experience with SONET network analyzers, oscilloscopes, function generators, logic analyzers, spectrum analyzers, digitizers, up/down-converters, ADC/DAC, National Instruments chassis-based equipment


  • V. Gusev-Lesau, E. Chen, W. A. Gruver, and D. Sabaz, “Embedded Linux for concurrent dynamic partially reconfigurable FPGA systems,” Proc. of the 2012 NASA/ESA Conference on Adaptive Hardware and Systems, Nürnberg, Germany, June 2012. (Received best paper award at the conference).
  • E. Chen, V. G. Lesau, D. Sabaz, L. Shannon, and W. A. Gruver, “Dynamic Partial Reconfiguration of FPGA Framework For Agent Systems,” Proc. of the 2011 Conference on Industrial Applications of Holonic and Multi-Agent Systems, Toulouse, France, Aug. 2011.
  • V. G. Lesau, D. Sabaz, and W. A. Gruver, "Embedded Linux for Hot Swapping Partially Reconfigurable Cores," SFU Exchange 2010 Conference, Vancouver, Canada, Tech. Poster, May 2010. (download)