The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design expected_ram.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 00000000FFFFFFF0, 00000000FFFFFFF1, 00000000FFFFFFF2, 00000000FFFFFFF3, ...). The design expected_ram.vhd has one read port. The read port has 1024 words of 64 bits each. The core uses a different clock enable than the input registers. The output of the read port is registered by clock.
The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.