In this course, you can use either VHDL, Verilog or SystemVerilog for your project. There are lots of references for either language; a few examples are shown below as a place to start. However, you might find a favourite if you do a bit of searching on your own. You can also probably find custom courseware copies of Douglas J. Smith's HDL Chip Design: A Pracitical Guide for Designing,
Synthesizing & Simulating ASICs and FPGAs Using VHDL or Verilog at
the bookstore.