ENSC 452/894 Advanced Digital System Design

Lab Information


The following links might be useful as you complete your project.
 

Available Lab Tutorials:

External Memory Example:

The following download will provide you with an example of how to include a memory controller for the DDR in a MicroBlaze system with a PLB [zip].

Using ChipScope Tutorial:

The following download is an updated version of the m12 lab module for using ChipScope done by Chris Fletcher at the ECE Dept at Berkeley. It will provide you with detailed instructions as to how to incorporate ChipScope into a design for debugging [pdf].

Old lab Tutorials (not completely updated):

Xilinx/Digilent Reference Designs Updated for EDK 8.2.02:

Note: To update the designs from EDK 7.1, you would need to modify the repository path ("ModuleSearchPath") in system.xmp for the local copy of the EDK Board Definition File (.xbd), Pcores, & Drivers before you open/upgrade the design in XPS if you have created a repository in your home directory.

Also Note: Upgrading will fail without a descriptive message if any of the files that need to be modified during the upgrade (such as MHS, MSS, XMP, and linker script files) are read-only. This is sometimes the case for zip archives distributed by Xilinx. Remember, you can change the editting properties of a file using the chmod command.

Remember these updated designs have a repository path that must be changed before compiling via "Project->Project Options..." as it's not valid for you.

Also, the DDR controllers in these modules are deprecated (being phased out of use). However, the new controller isn't backwards-compatible. Therefore, the old DDR controller has not been updated, but it should be updated. Please email me when any of you successfully update one of the designs with a DDR controller. Then I can take your updated and post it as the reference design.

Finally, these designs were created for EDK 8.2, so if I don't know if they will build or work. You will have to risk experimentation.

Sample OPB System:
opb_system.rar contains a basic XPS system (similar to lab 1) with a deprecated MicroBlaze and OPB bus. These pcores are considered deprecated by Xilinx, but should still work. Consider using this base system if you want to include an OPB pcore in your design and cannot get a PLB to OPB bridge working. It is recommended that you do NOT use the OPB if possible. Note: In order to use this system set the following preferences in XPS. In "Edit -> Preferences -> IP Catalog and IP Config Dialog" you must check "Display Deprecated IP Cores in IP Catalog " and "Display Available" IP cores (including legacy PLB/OPB cores) in "IP Catalog"

Reference Material on the XUP Virtex-II Pro Development System:

Reference Material on the Virtex-II Pro FPGA: Reference Material on Xilinx's Tools and Processor Cores:

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