%% File : driver_utils.tlc
%%
%% $Revision: 1.1.2.1 $
%% $Date: 2009/01/24 20:00:00 $
%%
%% Copyright 2001-2009 The MathWorks, Inc.
%%
%% Description: 
%%   TLC utilities for S12X block TLC files
%%   for the DEMO9S12XDT512 board.
%%

%function getPort(portNum) void
   %if ISEQUAL(portNum, 1)
       %return "PORTA"
   %else
       %return "PORTB"
   %endif
%endfunction

%function setBitVal(byte, bit, bitVal)
%%This function sets the value of the specified bit to bitVal which can be 0 or 1.

 %return "((%<byte>) & (~(1 << %<bit>)) | (%<bitVal> << %<bit>))"

%endfunction

%function getBitVal(byte, bit)
   %return "(((%<byte>) & ((1 << %<bit>))) >> %<bit>)"
%endfunction

%function pwmRegs()
   
   %createrecord regs { ...
       PWMPRCLK     "PWMPRCLK" ...
       PWMSCLB      "PWMSCLB" ...
       PWMCLK       "PWMCLK" ...
       PWMPOL       "PWMPOL" ...
       PWMCAE       "PWMCAE" ...
       PWMCTL       "PWMCTL" ...
       PWMPER2      "PWMPER2" ...
       PWMDTY2      "PWMDTY2" ...
       PWMCNT2      "PWMCNT2"  ...
       PWMPER3      "PWMPER3" ...
       PWMDTY3      "PWMDTY3" ...
       PWMCNT3      "PWMCNT3"  ...
       PWME         "PWME" ...
       }
  %return regs
   
%endfunction

%function encRegs()
   
   %createrecord regs { ...
       PACN32       "PACN32" ...
       PACN10       "PACN10" ...
       }
  %return regs
   
%endfunction

%function atdRegs(bank)
   
   %createrecord regs { ...
       ATDCTL0     "ATD%<bank>CTL0" ...
       ATDCTL1     "ATD%<bank>CTL1" ...
       ATDCTL2     "ATD%<bank>CTL2" ...
       ATDCTL3     "ATD%<bank>CTL3" ...
       ATDCTL4     "ATD%<bank>CTL4" ...
       ATDCTL5     "ATD%<bank>CTL5" ...
       ATDSTAT0    "ATD%<bank>STAT0" ...
       ATDSTAT1    "ATD%<bank>STAT1" ...
       ATDDIEN     "ATD%<bank>DIEN"  ...
       ATDPTAD     "ATD%<bank>PTAD" ...
       ATDDR0      "ATD%<bank>DR0" ...
       ATDDR1      "ATD%<bank>DR1" ...
       ATDDR2      "ATD%<bank>DR2" ...
       ATDDR3      "ATD%<bank>DR3" ...
       ATDDR4      "ATD%<bank>DR4" ...
       ATDDR5      "ATD%<bank>DR5" ...
       ATDDR6      "ATD%<bank>DR6" ...
       ATDDR7      "ATD%<bank>DR7" ...
   }
   %%assign regs = regs + "ATD0CTL0" + "ATD0CTL1" + "ATD0CTL2" + "ATD0CTL3"
  %return regs
   
%endfunction


%function sciRegs(bank)
   %createrecord regs { ...
       SCIBD      "SCI%<bank>BD" ...
       SCIBDH     "SCI%<bank>BDH" ...
       SCIBDL     "SCI%<bank>BDL" ...
       SCICR1     "SCI%<bank>CR1" ...
       SCICR2     "SCI%<bank>CR2" ...
       SCISR1     "SCI%<bank>SR1" ...
       SCISR2     "SCI%<bank>SR2" ...
       SCIDRH     "SCI%<bank>DRH" ...
       SCIDRL     "SCI%<bank>DRL" ...
   }
   %return regs
%endfunction


%function canRegs(bank)
   %createrecord regs { ...
       CANCTL0      "CAN%<bank>CTL0" ...
       CANCTL1      "CAN%<bank>CTL1" ...
       CANBTR0      "CAN%<bank>BTR0" ...
       CANBTR1      "CAN%<bank>BTR1" ...
       CANRFLG      "CAN%<bank>RFLG" ...
       CANRIER      "CAN%<bank>RIER" ...
       CANTFLG      "CAN%<bank>TFLG" ...
       CANTIER      "CAN%<bank>TIER" ...
       CANTARQ      "CAN%<bank>TARQ" ...
       CANTAAK      "CAN%<bank>TAAK" ...
       CANTBSEL      "CAN%<bank>TBSEL" ...
       CANIDAC        "CAN%<bank>IDAC" ...
       CANRXERR      "CAN%<bank>RXERR" ...
       CANTXERR      "CAN%<bank>TXERR" ...
       CANIDAR0      "CAN%<bank>IDAR0" ...
       CANIDAR1      "CAN%<bank>IDAR1" ...
       CANIDAR2      "CAN%<bank>IDAR2" ...
       CANIDAR3      "CAN%<bank>IDAR3" ...
       CANIDMR0      "CAN%<bank>IDMR0" ...
       CANIDMR1      "CAN%<bank>IDMR1" ...
       CANIDMR2      "CAN%<bank>IDMR2" ...
       CANIDMR3      "CAN%<bank>IDMR3" ...
       CANIDAR4      "CAN%<bank>IDAR4" ...
       CANIDAR5      "CAN%<bank>IDAR5" ...
       CANIDAR6      "CAN%<bank>IDAR6" ...
       CANIDAR7      "CAN%<bank>IDAR7" ...
       CANIDMR4      "CAN%<bank>IDMR4" ...
       CANIDMR5      "CAN%<bank>IDMR5" ...
       CANIDMR6      "CAN%<bank>IDMR6" ...
       CANIDMR7      "CAN%<bank>IDMR7" ...
       CANRXIDR0      "CAN%<bank>RXIDR0" ...   
       CANRXIDR1      "CAN%<bank>RXIDR1" ...
       CANRXIDR2      "CAN%<bank>RXIDR2" ...
       CANRXIDR3      "CAN%<bank>RXIDR3" ...
       CANRXDSR0      "CAN%<bank>RXIDSR0" ...
       CANRXDSR1      "CAN%<bank>RXIDSR1" ...
       CANRXDSR2      "CAN%<bank>RXIDSR2" ...
       CANRXDSR3      "CAN%<bank>RXIDSR3" ...
       CANRXDSR4      "CAN%<bank>RXIDSR4" ...
       CANRXDSR5      "CAN%<bank>RXIDSR5" ...
       CANRXDSR6      "CAN%<bank>RXIDSR6" ...
       CANRXDSR7      "CAN%<bank>RXIDSR7" ...
       CANRXDLR      "CAN%<bank>RXIDLR" ...
       CANRXTSRH      "CAN%<bank>RXTSRH" ...
       CANRXTSRL      "CAN%<bank>RXTSRL" ...
       CANRXTSR      "CAN%<bank>RXTSR" ...
       CANTXIDR0      "CAN%<bank>TXIDR0" ...   
       CANTXIDR1      "CAN%<bank>TXIDR1" ...
       CANTXIDR2      "CAN%<bank>TXIDR2" ...
       CANTXIDR3      "CAN%<bank>TXIDR3" ...
       CANTXDSR0      "CAN%<bank>TXDSR0" ...
       CANTXDSR1      "CAN%<bank>TXDSR1" ...
       CANTXDSR2      "CAN%<bank>TXDSR2" ...
       CANTXDSR3      "CAN%<bank>TXDSR3" ...
       CANTXDSR4      "CAN%<bank>TXDSR4" ...
       CANTXDSR5      "CAN%<bank>TXDSR5" ...
       CANTXDSR6      "CAN%<bank>TXDSR6" ...
       CANTXDSR7      "CAN%<bank>TXDSR7" ...
       CANTXDLR      "CAN%<bank>TXDLR" ...
       CANTXTBPR      "CAN%<bank>TXTBPR" ...
       CANTXTSRH      "CAN%<bank>TXTSRH" ...
       CANTXTSRL      "CAN%<bank>TXTSRL" ...
       CANTXTSR      "CAN%<bank>TXTSR" ...
   }
   %return regs
%% Note that Cosmic's definition for 16 individual registers {RXIDR0, TXIDR1, etc...} is       CAN0RXFG      "CAN%<bank>RXFG" ...
%% Note that Cosmic's definition for 16 individual registers {TXIDR0, RXIDR1, etc...} is       CAN0TXFG      "CAN%<bank>TXFG" ...
%endfunction