Defect & Fault Tolerance, 3D Stacked Chip, Wafer Scale Integration:

Glenn H. Chapman

This page contains the paper abstracts and full PDF versions of some publications on the Wafer Scale Integration concept. Click on the link to download pdf version.  Papers here are listed from most recent publication under journal or conference sections.
Note: These papers are for academic use only and are not available for distribution or publication for other purposes.

Refereed Journal Papers

G.H. Chapman and Benoit Dufort, "Using Laser Defect Avoidance to Build Large Area FPGA's", IEEE Design and Test, v5, 75-81, (Dec 1998) dtc98.pdf 128KB
Wafer-scale techniques of defect avoidance expend the complexity limits of field-programmable gate arrays by routing around flawed blocks to build working systems. Experiments on test FPGAs show that laser defect avoidance produces signal delays half those of active switches.
Y. Audet and G.H. Chapman, "Yield Improvement of a Large Area Magnetic Field Sensor Array using Redundancy Schemes", IEEE Tran. on VLSI Systems, v. 5, 28-33, (1997). vlsi97.pdf  208KB
The circuit design of a large area magnetic field sensor array (LAMSA) is described. This prototype is developed for applications in magnetic field mapping and tactile sensor arrays. To enable the production of such a large sensor system, redundancy schemes are implemented and a laser interconnection post fabrication technique is used for fault repairs. The design restructurable capabilities rely on local redundancy schemes for the sensor grid and global redundancy schemes for the surrounding control circuits. Experimental results obtained on a laser restructurable subarray of magnetic field sensor cells are shown. A study of the robustness of the local sensor grid redundancy schemes is presented.
Y. Audet and G.H. Chapman, "Effects of Scanning and Biasing Circuit Restructuring on the Calibration of Large Area Magnetic Field Sensor Array", IEEE Tran. on Components Packaging and Manuf. Technology - Part B, v. 20, 342- 348 (1997)
cpmt97.pdf   160KB
A large area magnetic field sensor array (LAMSA) has been designed and fabricated with built-in redundancy to achieve higher yield. The laser-link technology is used as the restructuring tool. The sensor system response is measured and calibrated with a general regression analysis method. Using the same method, an algorithm to evaluate the effects of the restructuring schemes of the biasing and scanning circuits on the response is developed. From measurements taken before and after restructuring, the influence of the row and the column scanning circuits restructuring are found to be weak, provided the resistance values of the formed laser-links are low, especially in the case of the column scanning circuit. Restructuring of the cascode current mirror acting as active load has shown the close dependence of the sensor cell responses on the transistor parameters. Helped by these restructuring schemes, the initial yield of 23 tested chips of size 6/spl times/3 mm was raised from 39 to 61%.
B. Dufort and G.H. Chapman, "Test Vehicle for a Wafer-Scale Field Programmable Gate Array", IEEE Trans. on Components Packaging and Manuf. Technology - Part B, v. 18, 431-437 (1995) cpmt95.pdf  588KB
A test vehicle for a wafer scale field programmable gate array (FPGA) has been designed which has the potential to significantly expand FPGA capabilities. A symmetrical RAM-programmable FPGA, look-up table-based logic block and segmented channel routing are used. In this paper, the practical problems inherent to wafer scale FPGA's are investigated: i.e., redundancy, power shorts, clock distribution, cell and bus testing, and inter-cell delay. The laser-link process is used to interconnect working cells and form a defect-free array of FPGA cells. The defect avoidance algorithm is designed to minimize the delay between working cells, an important parameter for FPGA users.
G.H. Chapman, M.J. Syrzycki, L. Carr, and B. Dufort, "Test Vehicle for a Wafer-Scale Thermal Pixel Scene Simulator" IEEE Trans. on Components, Hybrids and Manuf. Technology Part B, Invited paper, v. 17, 334-341 (1994). cmpt94.pdf  888KB
A chip sized test vehicle has been created to experiment with the technology and design required for two wafer scale thermal pixel displays: a Thermal Pixel Dynamic Scene Simulator and a Visual-to-Thermal Converter. The 4.7x4.7 mm device contains a 2x4 array of micromachined thermal pixels, optical detectors, A/D converters, digital pixel control circuitry, and laser links for interconnection. Laser produced defect avoidance schemes allowed testing and harvesting for global redundancy of the control circuitry and local transducer substitution. Also the laser linked signal buses flexibility was used to arrange the chip in different thermal pixel display configurations. Two chips were laser interconnected, one as fabricated and another where anisotropic etching had created a suspended plate holding the polysilicon resistor thermal pixels. From the electrical and laser interconnection points of operation there was no difference between the etched and unetched circuits.
M.J. Syrzycki, L. Carr, G.H. Chapman, and M. Parameswaran, "A Wafer- Scale Visual-to-Thermal Converter", IEEE Trans. on Components, Hybirds and Manuf. Technology, Invited paper, v. 16, 665-673 (1993). chmt93.pdf  1204KB
Wafer scale transducer arrays (WSTA's) containing multitransducer arrays combined with processing circuits are produced using a combination of CMOS technology, silicon micromachining, and laser interconnection techniques. A prototype wafer scale visual-to-thermal converter is being developed to convert a visual scene to thermal scene with the same resolution. The basic array is composed of transducer pixels, which combine photodetectors and thermal emitters as transducers together with signal conditioning and control circuitry, enabling 75%-50% local redundancy of system components. Unlike digital WSI designs, the WSTA redundancy approach is driven by regularity in transducer location and emphasizes local over global transducer sparing even when considering cluster defects. For WSTA, testing of functioning cells for WSI must be supplemented by compensating the transducer nonuniformities across the array.
G.H. Chapman, M. Parameswaran, and M.J. Syrzycki, "Wafer Scale Transducer Arrays", IEEE Computer, special issue on Wafer Scale Integration, v25, 4, 50- 56 (1992). computer92.pdf  627KB
A combination of post fabrication processing technologies enables new large area device applications. Previously wafer scale integrated circuits were successfully built using laser interconnection techniques after semiconductor fabrication.  Micromachining technology has generated several sensors using anisotropic etching of prefabricated CMOS chips. Combining these techniques enables the production of wafer scale transducer arrays (WSTAs). Potential applications include mapping variable distributions within an environment, injecting controlled energy matrices into media, placing several different transducers types within small physical area including combinations to generate signals and measure the results, plus self healing/repair for reliability.  WSTA design requirements are illustrated with a prototype, a wafer scale thermal-ppixel dynamic scene simulatoremploying laser linking for defect avoidance.
G.H. Chapman, "Laser Interconnection Techniques for Defect Avoidance in Large Area Restructurable Silicon Systems", Microelectronic Journal, 23, 267- 272 (1992).  microe92.pdf  420KB
Expanding IC sizes beyond the current chip limits for large area/wafer scale systems requires the use of circuit redundancy and defect replacement techniques. Aspects of a post fabrication defect avoidance process using a laser to make low resistance connections and cut lines in CMC's 3 and 1.2 micron technologies are described.
S.S. Cohen, P.W. Wyatt, and G.H. Chapman, "Laser-Induced Melting of Thin Conducting Films: Part I - the Adiabatic Approximation", IEEE Trans. Elec. Dev., 38, 2042-2050 (1991). ed91.pdf 848KB
The authors explore the thermal characteristics of an isolated metallic film which is subjected to a short pulse of laser radiation. The main feature of such an adiabatic system is that no steady-state solution is possible. This means that the molten zone dimensions depend on the pulse duration length and also on the temperature dependence of the influencing parameters (essentially, the thermal diffusivity). The authors use available models for the temperature-dependent conductivity and diffusivity to compare the theoretical results with experimental data obtained from a quasi-adiabatic system.
S.S. Cohen,  P.W. Wyatt, G.H. Chapman,  and J.M. Canter, "Melt-front velocity in laser-induced melting", J. Appl. Phys. v.67, 11, 6694-6700 (1990)  jap90c.pdf  731KB
Laser melting processes have been studied extensively, particularly for semiconductor substrates. Values for the velocity of the melt front have been determined by several experimental methods, and also calculated in numerical simulations of the melting processes. The velocity of the melt both during melting and recrystallization is of direct consequences for the material properties of the laser treated zone. Hence, a clear understanding of the physical parameters involved is essential. For laser pulses of a Gaussian shape, and whose duration is longer than a few tens of nanoseconds, expressions are derived for the melt-front velocity for the general case and for the limiting case of a point source. In either case the velocity turns out to be nonconstant. Hence, experimentally reported values may only be regarded as indicative of the maximum velocity achievable. The simple closed-form analytical expressions obtained in the present study are amenable for a direct analysis of relevant experimental results. Comparison made with some available data reveals a general agreement between theory and experiment. Ultra high-speed photography is one possible technique that may enable observation of the varying velocity of the lateral melt front
S.S. Cohen, P.W. Wyatt, J.M. Canter, and G.H. Chapman, "The Resistance of Laser Diffused Links", IEEE Trans. on Elect. Dev., ED-36, 1220-1225 (1989). ed89.pdf   412KB
Laser-diffused diode link (LDL) process makes possible a direct connection between devices at the substrate level, thus giving more flexibility to the overall system design. The electrical properties of these diode links are studied. Calculations based on a model for the resistance agree well with available experimental data. This model also provides physical insight on previously undetermined material properties such as the dopant diffusivity in the melt as a function of temperature.
F.M. Rhodes, J.J. Dituri, G.H. Chapman, B.E. Emerson, A.M. Soares, and J.I. Raffel, "A Monolithic Hough Transform Processor Based on Restructurable VLSI", IEEE Trans. on Pattern Analysis Mech. Intell., 10, 1, 106- (1988). pami88.pdf 508KB
The implementation of a Hough transform processor using a wafer-scale-integration technology, restructurable VLSI circuit is described. The Hough transform is typically used as a grouping operation in an image processing sequence. The transform discussed here groups pixels in order to extract linear features. This calculation is realized with a wafer-scale processor that allows a complete line extraction system to be integrated on a single PC board. Also discussed is the use of the CAD tools that allowed this processor to be realized without incurring silicon layout and processing overhead.
S.S. Cohen, P.W. Wyatt, G.H. Chapman, and J.M. Canter, "Laser Induced Diode Linking for Wafer-Scale Integration", IEEE Trans. on Elect. Dev., 35, 1533-1550 (1988). ed88.pdf  2108KB
Diodes formed by ion implantation and diffusion in a conventional CMOS process are positioned such that when desired they may be used to obtain an electrical link between two otherwise separate sections of the integrated circuit. Electrical connections so obtained enable the realization of wafer-scale ICs as demonstrated in  recent applications. They theory of laser-beam application to silicon is discussed and it is shown how the various beam and substrate parameters effect the properties of the diode links. Particular attention is paid to the important issue of the reflectivity from the composite system. Careful analytical examinations of the resulting molten zone properties have been performed to fully qualify the use of laser radiation in this technology. Both scanning electron microscopy and secondary-ion mass spectrometry were used to examine such parameters as the lateral and in-depth extension of the molten zone. In addition, electrical measurements were carried out. The results for the various observables compare well with the theoretical predictions.
J.M. Canter, G.H. Chapman, B. Mathur, M.L. Naiman, and J.I. Raffel, "A Laser-Induced Ohmic link for Wafer Scale Integration in Standard CMOS Processing", 44th Annual Device Research Conference, paper VB-6, IEEE Trans. Elec. Dev., ED-33, 11, 1861 (1986). ited86.pdf 146KB
Link structures used heretofore for wafer-scale integration have all required additional process steps not normally included in an MOS fabrication sequence. A new ”diode-link” has been developed that can be manufactured as part of a normal CMOS process. This structure consists of two diodes formed by implantation into a tub or substrate and bounded by the normal oxide windows used to define the source and drain regions of a transistor. These series-opposed diodes, separated by a gap of a few microns, constitute a high impedance until programmed. Heating by an incident laser beam causes a redistribution of dopant from the two implanted areas into the gap, forming an ohmic connection with a resistance ~45 ohm.
J.I. Raffel, A.H. Anderson, G.H. Chapman, K.H. Konkle, B. Mathur, A.M. Soares, and P.W. Wyatt, "A Wafer-Scale Digital Integrator Using Restructurable VLSI", IEEE Tran. on Elect. Dev., ED-32, 2, 479-486 (1985). jssc85.pdf  908KB
Wafer-scale integration has been demonstrated by fabricating a digital integrator on a monolithic 20 sq cm silicon chip, the first laser-restructured digital logic system. Large-area integration is accomplished by laser programming of metal interconnect for defect avoidance. This paper describes the technology for laser welding and cutting, the design methodology and CAD tools developed for wafer-scale integration, and the integrator itself.
J.I. Raffel, J.F. Freidin, and G.H. Chapman, "Laser Formed Connections Using Polyimide", Appl. Phys. Lett., 42, 705-706 (1983). apl83.pdf  3875KB
Electrical connections have been formed in a new lateral link structure which uses polyimide in the gap between, and overlapping, two aluminum electrodes. An argon ion laser, with a pulse width of 1 ms and power levels of about 2 W, was used to locally graphitize the polyimide. One kilohm connections were formed reliably in links ranging in width between 4 and 15 microns and gap length between 2 and 5 microns. This technique is the simplest yet proposed for restructuring the connections on an integrated circuit, after fabrication and test, in order to incorporate redundancy for yield improvement.
J.A. Yasaitis, G.H. Chapman, and J.I. Raffel, "Low Resistance Laser Formed Lateral Links", IEEE Elect. Dev. Lett., EDL-3, 7, 184-186 (1984). edl82.pdf 299KB
A new technique is described for reliably forming low resistance links by using a laser to bridge a lateral gap between two Al conductors deposited on insulating polysilicon. Resistances in the range of 1-10 ohms were achieved for gap widths of approximately 2-3 microns using 1 msec pulses from an argon laser. This technique should be ideally suited to implementing defect avoidance using redundancy in  large RAM’s and complex VLSI circuits. It requires a single level of metal and should provide higher density and lower capacitance when compared to alternative techniques.

Refereed Conference Proceedings

V. K. Jain and G.H. Chapman, “Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC”,  IEEE Int. Symposium on Defect and Fault Tolerance, pp 157 – 165, Washington, DC Sept 2006 dft06_3D.pdf 230KB
This paper discusses a defect tolerant and energy economized computing array for the DSP plane of a 3D heterogeneous system on a chip. We present the J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. The advantages of this approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. Moreover, many of the advanced algorithms, including the independent component analysis, can be systolically mapped to it. The paper discusses these coarse-grain cells in light of a new concept, namely multi-granularity, which simultaneously facilitates defect tolerance and reconfigurability. In particular, it is shown that the multipliers in these J-platform cells can benefit from an innovative block. Called multiplier building block (MBB), it can be used for defect tolerance as well as for configuring larger multipliers, thereby enhancing the yield and computational flexibility. An application example relating to defect tolerant visible sensors is described. We also discuss energy economization through the use of sleep transistor networks and multi-hop communication. The ultimate goal is to build such 3D heterogeneous sensor nodes with integrated processing and communications capability, and with provision for defect tolerance on the sensor plane as well as the multiple processing planes
G.H. Chapman, V.K. Jain and S. Bhansali, “Inter-Plane Via Defect Detection Using the Sensor Plane in 3-D Heterogeneous Sensor Systems”, Proc. IEEE Defect and Fault Tolerance Conf., pp 158-156, Monteray, CA Oct. 2005. dft05_3D.pdf 361KB
Defect and fault tolerance is being studied in a 3D Heterogeneous Sensor using a stacked chip with sensors located on the top plane, and inter-plane vias connecting these to other planes which provide analog processing, digital signal processing, and wireless communication/networking. The sensor plane contains four types of transducers: visible imager (Active Pixel Sensor), near IR and mid IR imager, and seismic and acoustic sensor arrays. This paper investigates ways of introducing defect and fault tolerance into the inter-plane via connections between the sensor and digital signal processing planes. The methodology detects failures in the inter-plane vias by inputting controlled signal patterns in each sensor type on the sensor plane. The sensor/via fault distribution in turn impacts the defect avoidance in the fault tolerant TESH network, which binds both the sensors and the processors that analyze and fuse the sensor plane data.  Fault tolerance in the design and fabrication of the micromachined IR bolometers is also studied.
V. K. Jain, S. Bhanja, G. H. Chapman, L. Doddannagari, and N. Nguyen1, “A Highly Reconfigurable Computing Array: DSP Plane of a 3-D Heterogeneous Sensor”, Proc. IEEE Int. SOC Conf. 2005, pp 243-246, Washington, DC Sept 2005. socc05.pdf  3,009KB
A 3D heterogeneous system on a chip using a stack of planes has recently been proposed. While the sensors are located on the top plane, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on a reconfigurable computing array for its DSP plane. The advantages of such an approach are high performance, small area and low power compared to FPGAs, and greater flexibility over ASICs. The authors presented the reconfigurable J-platform, which employs coarse-grain VLSI cells with high functionality, performance, and reconfigurability. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA/spl I.bar/PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the benefits of reduced external interconnect, much reduced design time, and manageable testability. The paper discusses these cells, including a new concept, namely multi-granularity. The methodology for mapping algorithms is illustrated by two important examples, FIR filtering of signals and images and the independent component analysis (ICA) algorithm. Finally, the paper discusses the issue of defect tolerance, which is critical in attaining reasonable yields making chip manufacture feasible.
V.K. Jain, S. Bhansali, and G.H. Chapman; and; “Inter-layer Vias and TESH Interconnection Network for 3-D Heterogeneous Sensor System on a Chip”, Proc. SPIE Defense and Security Symposium 2005, Unattended Ground Sensor Technologies and Applications VII, v5796, pp 306-317, Orlando, FL, April 2005. defense_spie05.pdf 399KB
In a previous paper we had described a novel concept on ultra-small, ultra-compact, unattended multi-phenomenological sensor systems for rapid deployment, with integrated classification-and-decision-information extraction capability from the sensed environment. Specifically, we had proposed placing such integrated capability on a 3-D Heterogeneous System on a Chip (HSoC). This paper amplifies two key aspects of that future sensor technology. These are the creation of inter-layer vias by high aspect ratio MPS (Macro Porous Silicon) process, and the adaptation of the TESH (Tori connected mESHes) network to bind the diverse leaf nodes on multiple layers of the 3-D structure. Interesting also is the inter-relationship between these two aspects. In particular, the issue of overcoming via failures, catastrophic as well as high-resistance failures, through the existence of alternative paths in the TESH network and corresponding routing strategies is discussed. A probabilistic model for via failures is proposed and the testing of the vias between the sensor layer and the adjacent processing layer is discussed.
V.K. Jain, S. Bhanja, G.H. Chapman, L. Doddannagari, N. Nguyen1, “A Parallel Architecture for the ICA Algorithm: DSP Plane of a 3-D Heterogeneous Sensor”, Proc. IEEE Int. Conf on Acoustics, Speech, and Signal Processing, v. 5,  pp 77-80, Philadelphia, PA, Mar. 2005. assp05.pdf 374KB
A 3D heterogeneous sensor using a stacked chip has recently been proposed. While the sensors are located on one of the planes, the other planes provide for analog processing, digital signal processing, and wireless communication. This paper focuses on its DSP plane, in particular on the implementation of the ICA (independent component analysis) algorithm in the DSP plane. ICA is a recently proposed method for solving the blind source separation problem. The objective is to recover the unobserved source signals from the observed mixtures without the knowledge of the mixing coefficients. We present a parallel architecture utilizing the reconfigurable J-platform, which employs coarse-gain VLSI cells. These include a universal nonlinear (UNL) cell, an extended multiply accumulate (MA PLUS) cell, and a data-fabric (DF) cell. The coarse-grain approach has the distinct advantages of reduced external interconnect, much reduced design time, and manageable testability. Additionally, the other algorithms needed for the 3D HSoC can also be mapped on to the same resources, by time multiplexing, thereby reducing the silicon area needed.
G.H. Chapman, V. Jain and S. Bhansali , “Defect Avoidance in a 3-D Heterogeneous Sensor”, Proc. IEEE Intern. Symposium on Defect and Fault Tolerence in VLSI Systems, pg. 67-75, Cannes, France Oct. 2004 dft04j.pdf  437KB
A 3D Heterogeneous Sensor using a stacked chip is investigated. While the sensors are located on one of the planes, the other planes provide for analog processing, digital signal processing, and wireless communication/networking -- with redundancy provisioned at each plane for defect tolerance. On the sensor plane four types of sensors are placed, namely visible imager (Active Pixel Sensor), infrared imager, seismic, and acoustic. The Active Pixel Sensor and IR Bolometer detectors are combined to create a multispectral pixel for aligned visible and infrared imaging.  An acoustic and seismic micromachined sensor array captures the corresponding signals from which the DSP plane computes the spectral and directional information.  For the APS/IR imagers fault tolerant cells and software interpolation methods are used for defect avoidance. For the acoustic/seismic array, the use of spare detectors combined with signal processing assure a high probability of successful reconfiguration as well as high accuracy functionality in spite of corresponding changes in detector positions. The sensor fault distribution in turn impacts the defect avoidance in the fault tolerant TESH network, which binds both the sensors and the processors that analyze and fuse the sensor plane data.
S. Bhansali, G. H. Chapman; E. G. Friedman; Y. Ismail; V. K. Jain; and P. R. Mukund, “3-D Heterogeneous Sensor System on a Chip”, Proc. SPIE Defense and Security Symposium 2004, Unattended/unmannded Ground, Ocean and Air Sensor Technologies and Applications VI, v5417, pg 413-424, Orlando, FL, April 2004. defense_spie04.pdf  465KB
This paper describes a new concept for ultra-small, ultra-compact, unattended multi-phenomenological sensor systems for rapid deployment, with integrated classification-and-decision-information extraction capability from a sensed environment. We discuss a unique approach, namely a 3-D Heterogeneous System on a Chip (HSoC) in order to achieve a minimum 10X reduction in weight, volume, and power and a 10X or greater increase in capability and reliability – over the alternative planar approaches. These gains will accrue from (a) the avoidance of long on-chip interconnects and chip-to-chip bonding wires, and (b) the cohabitation of sensors, preprocessing analog circuitry, digital logic and signal processing, and RF devices in the same compact volume. A specific scenario is discussed in detail wherein a set of four types of sensors, namely an array of acoustic and seismic sensors, an active pixel sensor array, and an uncooled IR imaging array are placed on a common sensor plane. The other planes include an analog plane consisting of transductors and A/D converters. The digital processing planes provide the necessary processing and intelligence capability. The remaining planes provide for wireless communications/networking capability. When appropriate, this processing and decision-making will be accomplished on a collaborative basis among the distributed sensor nodes through a wireless network.
V. Jain, and G.H. Chapman, “Level-Hybrid Optoelectronic TESH  Interconnection Network”, Proc IEEE Intern. Symposium on Defect and Fault Tolerence in VLSI Systems, pg 45-52, Boston, MA, Nov. 2003. dft03j.pdf  303KB
This paper discusses a hybrid optoelectronic scheme for a new interconnection network, "Tori  connected mESHes (TESH)".  The major features of TESH are the following: it is hierarchical, thus allowing exploitation of computation locality as well as easy expansion up to a million processors or devices,  it permits efficient VLSI/ULSI realization, it is designed to make use of redundancy for defect circumvention, and it appears to be well suited for 3-D  stacked implementation. Here, we discuss a novel extension to these capabilities through the provision of optical interconnections at the highest level, while keeping the lower levels  electronic through metal wires. The advantages of the resulting architecture, dubbed as Level-Hybrid Optoelectronic TESH, are the elimination of bottlenecks which typically occur at the highest level due to the aggregation of traffic, and the reduction of cost by using traditional wire channels at the lower levels -- where optical links are deemed unnecessary.
G.H. Chapman, "FPGA Design for Decimeter Scale Integration (DMSI)", IEEE Intern. Symposium on Defect and Fault Tolerence in VLSI Systems, pg. 64-72, Austin 1998. dft98p.pdf 92KB
Creating large area FPGA's is limited by defective sections and the maximum reticule print size (~3x3 cm). FPGA's are well suited for expanding into monolithic multiprint systems 2 to 9 times larger (5 - 10 cm square) we call DeciMeter Scale Integration (DMSI). DMSI expands system capacity, while producing many copies per wafer. Its design criteria is much simpler than the complex Wafer Scale Integration, but still uses defect avoidance routing around flawed blocks to build complete working systems. FPGA's have the main features required for successful DMSI systems: a repeatable cell, built in switchable flexible routing, high connectivity requirements between cell blocks, and flexibility with many potential applications. Modest changes at the periphery of FPGA's chips enables DMSI capability. Laser formed connections and cuts have proven effectiveness in bypassing fabrication time defects and creating defect free working wafer scale systems. The important DMSI criteria for laser defect avoidance is that defect free devices should need no correction. Depending on the DMSI size and current chip yields design defect avoidance requirements vary from simple row column substitution to cell by cell/row column substitution with redundant signal paths. Power shorts defects and how they are handled prove an important limitation on chip size.
G.H. Chapman, "Laser Applications to IC Defect Correction", Proceedings SPIE Photonics West: Lasers as Tools for Manufacturing of Durable Goods and Microelectronics, v 3274, pg 79-89, San Jose, 1998 pw98p.pdf 478KB
Integrated circuits complexity is controlled by defective sections which decrease IC yields and limit chip area to a few sq. cm. The post fabrication laser processing techniques of cutting lines and forming connections are effective in removing defects and enhancing fault tolerance in large VLSI circuits. Successful applications require designs which include redundant sections for substitution and the defect avoidance points built into the structure. Commercial devices have used cutting polysilicon lines to substitute rows and column blocks in memory chips (DRAM's), microprocessor's cache memory and Field Programmable Gate Arrays. More complex wafer scale systems of 25 sq cm have been built using combinations of additive connections and line cutting to route signals around defective areas thus creating defect free large working systems. These used laser diffused links consisting of two conductively doped lines in silicon separated by a gap. An argon ion laser pulse (100 microsec., 2 W, 1.2 micron FWHM) spreads dopant throughout the gap generating ~70 ohms connections. Metal links of two metal lines, separated by 1 micron), covered by intermetal insulator. A laser pulse expands the metal, fractures the SiO2 between the lines, and forces molten metal to make < 3 ohms connections. Both links show lower impedance alternative like active transistor switches (~3-6 Kohm).
G.H. Chapman and B. Dufort, "Laser Correcting Defects to Create Transparent Routing for Large Area FPGA's", Procceedings ACM/SIGDA Int. Symposium on FPGA'97, pg 17-24, Monterey CA (Feb. 1997). fpga97p.pdf 262KB
Creating large area FPGA's is limited by the presence of defective sections. The techniques developed in wafer scale work solve this problem by using defect avoidance routing around flawed blocks to build complete working systems. FPGA's have the main features required for successful defect avoidance systems: a repeatable cell, built in need for switchable flexible routing and high flexibility with potentially large number of applications. Laser formed connections and cuts have proved to be effective in bypassing fabrication time defects and creating defect free working systems up to wafer scale in area. Power shorts and clock distribution errors can effectively be eliminated using these laser links. In addition it is important to minimize signal delays so the bypassing of the defective cells is nearly invisible. Experiments on a small test FPGA shows defect avoidance routing using laser link structures generates delays which are about half those obtained by the active switches required for the FPGA's operation. Thus laser defect avoidance after fabrication removes the errors creating a large area FPGA whose defective cell distribution is nearly unseen by the user.
G.H. Chapman and Benoit Dufort, "Laser Defect Correction Application to FPGA Based Custom Computers" Proceedings IEEE FPGA's for Custom Computing Machines (FCCM'97), pg 240-241, Napa Valley CA (1997).  fpccm97.pdf 168KB
The complexity and speed of monolithic FPGA based custom computers has been set by the presence of defective sections which limit chip area. Test FPGAs show that laser link defect avoidance routing around flawed blocks generates delays >50% of active switches, making the error cell distribution nearly invisible.
G.H. Chapman and B. Dufort, "Making Defect Avoidance Nearly Invisible to the User in Wafer Scale Field Programmable Gate Arrays", Proceedings IEEE International Symposium on Defect and Fault Tolerence in VLSI Systems, pg 11- 19, Boston, MA, (Nov. 1996). dft96.pdf 355KB
Field programmable gate arrays have the main features required for interesting wafer scale systems: high flexibility with potential large number of applications, a repeatable cell, and a built in need for switchable flexible routing. Wafer scale work must involve routing around defective cells to build the large system. However, it  important to minimize signal delays so the bypassing of the defective cells is invisible. Experiments on a small test FPGA shows defect avoidance routing using laser link structures produces delays which are about half those produced by the active switches required for the FPGA's operation.
Y. Audet and G.H. Chapman, "Effects of Scanning and Biasing Circuit Restructuring on the Calibration of Large Area Magnetic Field Sensor Array", Proceedings IEEE Int'l Conf. on Innovative Systems in Silicon 1996, pg 61-70, Austin, TX, (Oct. 1996).
isis96a.pdf  507KB
A large area magnetic field sensor array has been designed and fabricated with built-in redundancy using the laser-link technology as a restructuring tool. The sensor system response is measured and calibrated with a general regression analysis method. An algorithm to evaluate the effects of the restructuring schemes of the biasing and scanning circuits on the response is presented. From these first results, influence of the biasing circuit on the sensitivity of the sensor system is established and modification in the post-processing technique to reduce chip damage are required.
G.H. Chapman, D.E. Bergen and K. Fang, "Wafer-Scale Integration Defect Avoidance Tradeoffs between Laser Links and Omega Network Switching", Int. Workshop on Defect and Fault Tolerance pg 37-45, Lafayette, LA (1995)  dft95.pdf 577KB
Area, signal delay, and power consumption requirements are obtained in both 3 micron and 1.5 micron CMOS for two wafer scale defect avoidance methods: laser linking and active switching. In laser linking, focused laser power is used at each site to interconnect and cut bus lines. Active switching elements, such as the Omega network, enable real-time defect bypassing for self healing reconfigurations. Comparisons using simulations and fabricated device measurements of an Omega switch relative to laser links shows the area ranges from 5 to 11 times larger (respectively for the 1.5 and 3 micron processes), it requires an extra 18 to 25 nsec of signal delay and cell drivers to consume 60% more power than the laser links. Laser linked signal paths are so much faster than active switches that they effectively bypass failed switches without introducing significant extra delay. Thus a superior defect avoidance switch combines laser links and the Omega switch into a single unit.
Y. Audet and G.H. Chapman, "Robust Design of a Large Area Magnetic Field Sensor Array", Proc. IEEE Int. Conf. on Wafer-Scale Integration '95, 207-216, San Francisco (1995).  wsi95au.pdf  539KB
Design of a Large Area Magnetic Field Sensor Array (LAMSA) using redundancy schemes concurrently with the laser link technology for fault repairs is presented. Experimental results obtained on a laser restructurable subarray of three magnetic field sensor cells are shown. An experimental yield measurement method to determine parameters of two yield detractors is described. These parameters obtained from regular sized VLSI chips are used to predict the yield of larger sensor array designs implemented with redundancy.
B. Dufort and G.H. Chapman, "Test Vehicle for a Wafer-Scale Field Programmable Gate Array", Proc. IEEE Int. Conf. on Wafer-Scale Integration '95, 33-42, San Francisco (1995).  wsi95du.pdf 437KB
A test vehicle for a wafer scale FPGA has been developed. A symmetrical RAM-programmable FPGA, lookup table based logic block and segmented channel routing are used. In this paper, we emphasize on the practical problems inherent to wafer scale FPGAs: redundancy, power shorts, clock distribution, cell and bus testing. The laser-link process is used to interconnect working cells and form a defect free array of FPGA cells. The defect avoidance algorithm is designed to minimize the delay between working cells, an important parameter for FPGA users.
M.J. Syrzycki, M. Parameswaran, and G.H. Chapman, "Integrated Transducer Systems", Proceedings Czujniki Optpelecktroniczne I Eleektroniczne, Warsaw, Poland, May 22-25 1994, Proceedings SPIE, v 2634, 2-15 (1995) pol94.pdf  1727KB
In the paper we discuss possible solutions to problems pertaining the implementation of integrated transducer systems, based on examples of WSI image transducers magnetic field sensors and tactile sensors arrays as well as arrays of chemical sensors. We also present the issues common to large area transducer arrays, such as building-in redundancy into WSI transducer arrays, and frequency domain circuits for the future communication pathway in integrated transducer systems. Advantages of standard CMOS technology, enhanced with various post-fabrication processes such as silicon micromachining and laser linking, are also stressed.
G.H. Chapman, "Laser Processes for Defect Correction in Large Area VLSI Systems", invited paper, Proceedings IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 106-114, Montreal (1994). dft94.pdf 638KB
The post fabrication laser processing techniques of cutting lines and forming connections is effective in removing defects and enhancing fault tolerance in large area VLSI circuits. Successful applications require designs which include redundant sections for substitution and defect avoidance points built into the structure. To minimize the area cost and post fabrication error correction time requires careful attention to the physical aspects of the system including location of the defect avoidance sites and testing considerations. The resulting gains range from significant increases in smaller chip yields to significant expansion of useable circuit area in the large area/wafer scale region with circuit sizes greater than 25 sq. cm.
G.H. Chapman, M.J. Syrzycki, L. Carr, and B. Dufort, "Test Vehicle for a Wafer-Scale Thermal Pixel Scene Simulator", Proc. IEEE Int. Conf. on WaferScale Integration '94, 1-10, San Francisco (1994). wsi94g.pdf  496KB
A chip sized test vehicle has been created to experiment with two wafer scale thermal pixel displays: a Thermal Pixel Dynamic Scene Simulator and a Visual-to-Thermal Converter. The 4.7x4.7 mm device contains a 2x4 array of micromachined thermal pixels, optical detectors, A/D converters, digital pixel control circuitry, and laser links for interconnection. Laser produced defect avoidance schemes allowed testing and harvesting for global redundancy of the control circuitry and local transducer substitution. Also the laser linked signal buses flexibility were used to arrange the chip in different thermal pixel display configurations. Two chips were laser interconnected, one as fabricated and another where anisotropic etching had created a suspended plate holding the polysilicon resistor thermal pixels. From the electrical and laser interconnection points operation there was no difference between the etched and unetched circuits.
G.H. Chapman and K. Fang, "Comparison of Laser Link Crossbar and Omega Network Switching for Wafer-Scale Integration Defect Avoidance", Proc. IEEE Int. Conf. on Wafer-Scale Integration '94, 352-361, San Francisco (1994). wsi94k.pdf 418KB
A study is presented of the design tradeoffs between two wafer scale defect avoidance methods: laser linking and active switches. Laser linking methods use laser processing to make signal line connections and cuts. Alternately active transistor switching elements, like the Omega network, can circumvent defects. WSI systems would benefit from a combination of both methods. The requirements of both for silicon area, signal delay, power consumption, probable switch yield and defect avoidance flexibility are considered. As an experimental vehicle an 8x8 Omega network and laser link crossbar switch was fabricated and tested.
Y. Audet and G.H. Chapman, "Design of a Large Area Magnetic Field Sensor Array", Proc. IEEE Int. Conf. on Wafer-Scale Integration '94, 273-281, San Francisco (1994). wsi94au.pdf 406KB
The circuit design of a Large Area Magnetic Field Sensor Array (LAMFSA) using CMOS 3 /spl mu/m process is described. This prototype is developed mainly for application in magnetic field mapping and tactile array sensors. In order to enable the production of such a device, redundancy schemes are implemented and a laser interconnection post fabrication technique is used. The basic sensing cell consists of a double drain/double source MOS magnetic field sensor (MAGFET). The design architecture is strongly influenced by the sensor function and the defect avoidance criteria. Aided by SPICE, test and reconfiguration issues involved in the post fabrication processing are described.
Y. Audet and G.H. Chapman, "Sensitivity Optimization of Double Drain/Double Source and Triple Drain/Triple Source MOS Magnetic Field Sensors", Proceedings of CCVLSI'93, 7:40-44, Banff, Alb (1993). ccvlsi93a.pdf 275KB
New double drain/double source and triple drain/triple source merged Mosfets have been developed for magnetic field sensors arrays (Magfet arrays). Experimental results are being compared with a simple versatile model using finite element circuits irnplemented by SPICE. Sensitivity distributions along arrays of double drain/double source and triple drain/triple source merged Magfet magnetic field sensing cells have been observed so confirmed by the SPICE model.
M.J. Syrzycki, L. Carr, G.H. Chapman, and M. Parameswaran, "A Wafer-Scale Visual-to-Thermal Converter", International Conf. on Wafer Scale Integration, 1-10, San Francisco, CA (1993). wsi93s.pdf  630KB
Wafer scale transducer arrays (WSTAs) containing multi-transducer arrays combined with processing circuits are produced using a combination of CMOS technology, silicon micromachining and laser interconnection techniques. A prototype wafer scale visual-to-thermal converter is being developed to convert a visual scene to thermal scene with the same resolution. The basic array is composed of transducer pixels, which combine photodetectors and thermal emitters as transducers, together with signal conditioning and control circuitry. The WSTA redundancy approach is driven by regularity in transducer location and emphasizes local over global transducer sparing.
G.H. Chapman & R.F. Hobson, "Algorithmic Bus and Circuit Layout for Wafer-Scale Integration and Multichip Modules", Int'l Conf. on Wafer Scale Integration, 137-146, San Francisco, CA (1993). wsi93h.pdf  394KB
In both laser-link-oriented wafer scale integration (WSI) and multichip modules (MCMs), arrays of devices may be ordered in such a way that the actual physical position of devices is extremely important. Traditional graphic-based design systems are not well suited for such applications. Examples are presented illustrating the effectiveness of a C-based design language (CDL) for WSI laser-link bus placement and MCM chip placement and interconnection. A brief description of the CDL platform is included.
G.H. Chapman, M. Parameswaran, and M.J. Syrzycki, "A Wafer Scale Dynamic Thermal Scene Generator", Proc. International Conf. on Wafer Scale Integration, San Francisco, CA, 300-309 (1992). wsi92.pdf 548KB
As a prototype WSTA (wafer scale transducer array), a wafer scale dynamic thermal scene generator is being developed to generate a controllable infrared (IR) image for use in calibrating IR detector arrays. The basic array consists of two cell types, one being a thermal pixel containing a poly Si resistor sitting on a suspended oxide bridge. The second cell contains the addressing, intensity register, and current level control electronics. Unlike digital WSI designs, WSTA redundancy efforts must emphasize local over global transducer sparing even considering cluster effects. Granularity in transducer location drives local pixel cells into creating small subtransducer arrays, with multiple devices at each site turned on for a single pixel. The control cells are allowed a larger substitution area than the thermal transducer.
G.H. Chapman, J.M. Canter, and S.S. Cohen, "The Technology of Laser Formed Interactions for Wafer-Scale Integration", Proc. International Conf. on Wafer Scale Integration, ed. E. Swartzlander and J. Brewer, 21-29, San Francisco, CA (1989).
wsi89.pdf  468KB
Restructurable VLSI wafer-scale circuits have been built using two methods, both using laser energy to create low resistance connections between bus lines on already existing circuits. In one technique verticle connections of about 10 Omega are made up from top metal, through silicon nitride, to first metal lines. The other involves melting of silicon in the gap between two implant regions, with the lateral diffusion of dopants creating connections of about 100 Omega . Details of the linking structures, their characteristics, and the apparatus used to interconnect them are described.
T.O. Herndon, J.A. Burns, and G.H. Chapman, "Planer Vias by Ion Implantation", Proc. Sixth IEEE VLSI Multilevel Interconnect Conf., 322-328, Santa Clara, CA, (1989) vlsimic89.pdf  480KB
A technique is described whereby implantation of silicon through a mask into the intermetal insulator modifies the insulation. After deposition and definition of the upper metal, the implanted regions between metal levels act as voltage programmable links. Application of a voltage between upper and lower metal electrodes causes the implanted insulation to become conductive, producing a low-resistance, planar, vertical connection.  Alternatively, these implanted areas can be rendered conducting by exposure to a focused laser beam.
G.H. Chapman, J.I. Raffel, J.M. Canter and R.M. Rhodes "Advances in Laser Link Technology for Wafer-Scale Circuits", in "Wafer Scale Integration II: Proceedings of the Second I.F.I.P Workshop on Wafer Scale Integration", R.M. Lea editor, North-Holland, Oxford, 217-225 (1988). ifip88c.pdf  477KB
Five different wafer-scale integrated circuits have been produced in the past few years using the restructurable VLSI process. This technique employs a laser pulse to make low resistance connections between electrically isolated metal lines, or to segment such lines with cuts. Thus, operable circuit elements may be interconnected and defective ones circumvented. The RVLSI design approach is based on partitioning a system into redundant blocks, or cells, and building a wafer with a redundancy factor of about 100%. Outside these cells there is a grid of wafer-length, two-level metal bus lines, with laser linking devices at selected intersections. After wafer fabrication in a nearly standard CMOS process, the circuits are probed to obtain a map of the operable cells and the lines are tested using capacitance techniques to determine shorted or open metal areas. Assignment and routing CAD programs then generate from these defect maps, the interconnection paths needed to implement the desired wafer-scale system. After sawing and packaging, the wafer is processed on a laser linking system consisting of an X-Y table driven by a linear induction motor with laser interferometric position control (accurate to <0.5 microns). Under computer control, the laser links and cuts are used to interconnect the operable elements via the bus grid, and to add them to the power bus.
G.H. Chapman, "Laser Linking Technology for VLSI", in "Wafer Scale Integration", C. Jesshope, and W. Moore, Editors, Adam Higer, Bristol and Boston pub., Bristol, 204-215 (1986). wwsi86.pdf  620KB
The laser-linking technology associated with the restructurable VLSI approach to wafer scale integration at MIT Lincoln Laboratory uses a mechanically shuttered cw argon laser to deliver energy pulses to wafer locations determined by a precision table computer controlled in x – y and z directions. In this approach, the focused laser spot is employed to make vertical microwelds for bus and power connections, to segment lines or remove defects and to test optically the interconnections paths (Chapman et al 1984). This section covers some of the advances that have been made in the laser-linking and -cutting processes that were used to produce three fully functioning wafer scale CMOS systems which were fabricated on 3-inch wafers
J.I. Raffel, A.H. Anderson, G.H. Chapman, S.G. Garverick, K.H. Konkle, B. Mathur, and A.M. Soares, "A Wafer-Scale Digital Integrator", Proc. IEEE Int. Sym.on Circuits and Systems, 781-784, May (1983). iscs83a.pdf 1751KB
Two-level metal interconnect wiring on a silicon wafer has been restructured using a laser to form and break connections. A system of 16 logic cells each comprising a 4-bit buffered counter has been restructured to form a digital integrator by wiring around defective cells using an automated assignment and linking system to locate and control the 500 links and 100 cuts required to define the interconnect wiring nets.
J.I. Raffel, M.L. Naiman, R.L. Burke, G.H. Chapman, and P.G. Gottschalk, "Laser Programmed Vias for Restructurable VLSI", Int. Elect. Dev. Meet. Tech. Digest, 132-135, Washington, DC (1980). iedm80a.pdf 360KB
A techniques has been developed which uses a laser to form selectively connecting vias between two levels of aluminum wiring on a silicon wafer. The same laser can remove metal thus providing a capability of either adding or. deleting connections in fully fabricated devices. Experiments have been performed with a commercial IC mask trimmer using a 100 nsec pulse width neodymium YAG laser. Single pulses provide low resistivity connections with no thermal annealing required. The inter-metal insulating layer is formed by sputtering 2600 A of amorphous silicon. Chains containing forty 6.3 micron x 6.3 micron vias between first and second level metal were successfully connected width low resistances and high current capability. At a thickness of 4400 A of thermal oxide breakthrough to the substrate limits the operating margins on laser power to only 10% above the power for 100% via contacts; at one micron breakthrough is eliminated entirely
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